Following the ACM TechTalk, David Patterson was kind enough to answer some additional questions we were not able to get to during the live event. These questions and answers are presented below:
Q: Any thoughts about recent IBM announcement to open-source PowerPC architecture? Comparison with RISC-V?
A: Glad to see they’re following our lead, which adds evidence to the viability of open architectures. I really like simple architectures, and Power is a long way from that, more like ARMv8 in complexity. Both are so complicated that you can’t find anyone writing a book to explain the architectures. In contrast, our RISC-V book is just 100 pages. (http://riscvbook.com/)
Q: Dave, do you envision a “soft IP core” for RISC-V for FPGA? E.g., ARM soft IP for Xilinx.
A: There are several available already. Jan Grey has more than 1000 RISC-V cores on a Xlinx FPGA, amazingly enough.
GRVI Phalanx: A Massively Parallel RISC-V® FPGA Accelerator Framework
Q:Thoughts on why Intel/HP chased the “white whale” of Titanium for so long? Did they think that smart compilers would handle this micro-parallelism when compilers haven’t been able to solve the general parallelism problem?
A: Our CACM paper mentions it, but basically they postulated an architecture based on compiler technology advances that weren’t achievable, and so the debate was settled by the marketplace, to HP and Intel’s misfortune.
Q; Where does RISC-V fit on the CPU/GPU/DomainSpecificUnit spectrum?
A: RISC-V is a general purpose CPU like the x86 (C compiler and so on) but the architecture sets aside opcoode space for developers to add custom instructions for DSA as needed. Many prior architectures basically ran out of opcode space, making them hard for new DSA instructions.
Q: You didn’t include HW disaggregation in the picture, especially for cloud infrastructure. Don’t you think changing the archi of a server through HW disaggregation is also a big promise?
A: Hardware disaggregation—memory is independent from storage which is independent from computation—might happen, and it could lead to more efficient datacenters, but it is not a sure thing. So far lots of people are still filling datacenters with conventional servers.
Q: How to learn deeply about out-of-order CPU?
A: Probably many web sites try to explain it, but if not, our textbook does.
Q: Any hope for general architecture that combines general purpose architecture and domain specific?
A: Certainly Intel is trying with their ever expanding SIMD instruction set; there is a version for deep learning, for instance. Depending whether you think GPUs are general purpose, they are definitely adding features just for machine learning. Hard to know how far they will get; once again, the marketplace will determine.
Q: Adding custom instruction is not going from RISC to CISC?
A: Good question. The slight difference is that the RISC-V compilers are all based on a simple ~50 instruction core, and you don’t need any complex instructions to run a large software stack. The “CISC” instruction are optional on a per application basis, and not every future RISC-V computer has to offer this instruction foreover, as in the case of SIMD instructions for x86. Thus, you can still build a tiny core for IoT based on RISC-V without the CISC instruction screwing things up, more or less in all future implementation as in conventional architectures.
Q: What about technologies like carbon nanotubes?
A: Just yesterday there was an announcement by MIT that put it into perspective. They built a cut-down RISC-V core in CNT (16-bit data path) but instructions are still 32-bits in 14,000 transistors. (32-bit RISC-I was about 40,000 transistors). They got it to work, but it only ran at 10 KHhz (that’s KHz, not MHz, and not GHz). CNT is a long ways off.
16-bit RISC-V processor made with carbon nanotubes